(1) Field
This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms.
(2) General Background
Traditional Application Specific Integrated Circuit (ASIC) design methods and the “Fabless Integrated Circuit (IC)” business model have worked well for the personal computer (PC) industry for many reasons. The primary reason is that PC design requirements typically do not radically change from one product to another. In comparison, the wide spread proliferation and constant evolution of the communications standards cause product design requirements of digital communication products to significantly change from one product to the next product. As a result, the overhead resulting from applying ASIC design methods and the “Fabless IC” business model to Digital Communications products are far more excessive.
Generally, the value that a typical digital communication semiconductor company following the “Fabless IC” business model offers is concentrated in the design content of the IC. Typically, the semiconductor technology offered by many fabless semiconductor companies is merely a redesign and re-packaging of components that the companies have previously designed. These fabless companies generally expend disproportional monetary and human resources to re-package various communication components to produce products. Therefore, chip design cycles normally assume a substantial portion of the total cost of final products.
There are several other significant shortcomings of the “Fabless IC” business model and ASIC design methods when applied to the development of digital communication products. These shortcomings arise basically from the fact that the implementation of digital communication products typically includes embedded software that is not well integrated into the design process. Some exemplary shortcomings may include:
Lack of a unified hardware (HW) and software (SW) design approach, leading to difficulties in verifying the integrated design, and hence incompatibilities across the hardware and software boundary.
Tendency to define a priori a partitioning of hardware and software, leading to rigid and sub-optimal designs.
Lack of well-defined design flow, making specification revision difficult and hence impacting time-to-market.
Lack of built-in techniques within the design process to promote reusability and portability, preventing timely reaction to market trends and leading to the inability to leverage attained market position.
As a result, it is desirable to have a new approach to communication processor design and design methodology that could overcome the aforementioned shortcomings and that is more compatible with the market evolution cycles in the digital communication semiconductor industry.